1. FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to improved methods and apparatus for burn-in stress testing of semiconductor memory devices.
2. DESCRIPTION OF THE RELATED ART
As semiconductor memory devices become more highly integrated, defects in memory cells are increased due to processing problems and the like. Furthermore, as a chip becomes increasingly highly integrated, the size of each individual transistor of the chip is decreased. As a result, when the external power voltage is applied to the size-reduced transistor, the stress thereof is increased, thereby forming a strong electric field, which degrades the transistor. Thus, in order to attain reliability of a semiconductor chip by initially detecting defects in memory cells, a burn-in stress is performed upon completion of the chip. This is done by applying a high-voltage which exceeds the maximum external power voltage stipulated in the chip specification to the gate of a memory cell transistor, at a high-temperature and for a relatively long time, e.g. several minutes. Thus, the stress applied to various elements of the chip is increased, thereby facilitating initial detection of defects. Conversely, a device that survives this burn-in stress testing is more likely to be reliable in normal use.
The stressing method is generally performed in the following manner. In known DRAM devices, only a single wordline is asserted (H) during a row address strobe (RAS/) cycle, although the same wordline may be simultaneously asserted in several arrays of memory cells within the same device. FIG. 1 shows the architecture of a conventional 4-Mbit DRAM, in which four memory cell sub-arrays are disposed in a matrix, each sub-array having 1024 rows. The sub-arrays are simultaneously enabled. In other words, when a row address strobe signal (RAS/) is asserted, and the first row is addressed, each first row of the respective memory cell sub-arrays 1M, 1M', 1M" and 1M'" becomes active. When the (RAS/) is in the precharge state, each first row of the respective sub-arrays 1M, 1M', 1M" and 1M'" is reset.
Then, when the next (RAS/) is asserted, each second row of the respective sub-arrays 1M, 1M', 1M" and 1M'" becomes active. In this manner, each row of the arrays is sequentially accessed to carry out the burn-in test. The process is thorough but time consuming. For example, if a burn-in time is set to about 72 hours, which may vary according to manufacturers and chip characteristics, a high voltage stress is applied to each row (and thus to each access transistor) for about 4.2 minutes (72 hours.div.1024). The above-described burn-in test procedure causes a substantial increase in the burn-in time when the number of memory cells disposed in the chip increases. In the case of a 16-Mbit DRAM, in order to allow a stress time of about 4.2 minutes to an access transistor, a burn-in time of 288 hours (72.times.4) is required, and in the case of a 64-Mbit DRAM, a burn-in time of 576 hours (72.times.8) is required. This time frame is not practical.
In the above-described prior art, the burn-in test in respective access transistors connected to each wordline is performed while memory cell arrays of the semiconductor memory device are sequentially activated from the first wordline. In other words, the burn-in stress time is excessive because it proceeds row-by-row, one row at a time. Moreover, since the testing is done one row at a time, the stress time increases linearly with increases in the depth of the memory, as illustrated above.